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19 ?general purpose dielectric for ceramic capacitors ?eia class ii dielectric ?temperature variation of capacitance is within ?5% from -55? to +85? ?well suited for decoupling and filtering applications ?available in high capacitance values (up to 100?) x5r dielectric general specifications part number (see page 2 for complete part number explanation) general description % capacitance -60 -40 -20 0 +20 +40 +60 +80 temperature c temperature coefficient 20 15 10 5 0 -5 -10 -15 -20 typical electrical characteristics insulation resistance (ohm-farads) 1,000 10,000 100 0 insulation resistance vs temperature 0 20 120 40 60 80 temperature c 100 2220 size (l" x w") 6 voltage 4 = 4v 6 = 6.3v z = 10v y = 16v 3 = 25v d = 35v 5 = 50v d dielectric d = x5r 107 capacitance code (in pf) 2 sig. digits + number of zeros m capacitance tolerance k = ?0% m = ?0% a failure rate a = n/a t terminations t = plated ni and sn 2 packaging 2 = 7" reel 4 = 13" reel 7 = bulk cass. 9 = bulk a special code a = std.
20 x5r dielectric specifications and test methods parameter/test x5r specification limits measuring conditions operating temperature range -55? to +85? temperature cycle chamber capacitance within specified tolerance 2.5% for 50v dc rating freq.: 1.0 khz 10% dissipation factor 3.0% for 25v dc rating voltage: 1.0vrms .2v 3.5% for 16v dc rating for cap > 10 ?, 0.5vrms @ 120hz 5.0% for 10v dc rating insulation resistance 100,000m ? or 500m ? - ?, charge device with rated voltage for whichever is less 120 5 secs @ room temp/humidity charge device with 300% of rated voltage for dielectric strength no breakdown or visual defects 1-5 seconds, w/charge and discharge current limited to 50 ma (max) appearance no defects deflection: 2mm capacitance test time: 30 seconds resistance to variation ?2% flexure dissipation meets initial values (as above) stresses factor insulation initial value x 0.3 resistance solderability 95% of each terminal should be covered dip device in eutectic solder at 230 5? with fresh solder for 5.0 0.5 seconds appearance no defects, <25% leaching of either end terminal capacitance variation ?.5% dip device in eutectic solder at 260? for 60 dissipation meets initial values (as above) seconds. store at room temperature for 24 2 resistance to factor hours before measuring electrical properties. solder heat insulation meets initial values (as above) resistance dielectric meets initial values (as above) strength appearance no visual defects step 1: -55? 2 30 3 minutes capacitance variation ?.5% step 2: room temp 3 minutes dissipation meets initial values (as above) step 3: +85? 2 30 3 minutes thermal factor shock insulation meets initial values (as above) step 4: room temp 3 minutes resistance dielectric meets initial values (as above) repeat for 5 cycles and measure after strength 24 2 hours at room temperature appearance no visual defects capacitance variation ?2.5% dissipation initial value x 2.0 (see above) load life factor insulation initial value x 0.3 (see above) resistance dielectric meets initial values (as above) strength appearance no visual defects capacitance variation ?2.5% load dissipation initial value x 2.0 (see above) humidity factor insulation initial value x 0.3 (see above) resistance dielectric meets initial values (as above) strength charge device with 1.5x rated voltage in test chamber set at 85? 2? for 1000 hours (+48, -0). note: contact factory for specific high cv devices that are tested at 1.5x rated voltage. remove from test chamber and stabilize at room temperature for 24 2 hours before measuring. store in a test chamber set at 85? 2?/ 85% 5% relative humidity for 1000 hours (+48, -0) with rated voltage applied. remove from chamber and stabilize at room temperature and humidity for 24 2 hours before measuring. 1mm/sec 90 mm
21 x5r dielectric capacitance range preferred sizes are shaded size 0201 0402 0603 0805 soldering reflow only reflow only reflow only reflow/wave packaging all paper all paper all paper paper/embossed (l) length mm 0.60 0.03 1.00 0.10 1.60 0.15 2.01 0.20 (in.) (0.024 0.001) (0.040 0.004) (0.063 0.006) (0.079 0.008) (w) width mm 0.30 0.03 0.50 0.10 0.81 0.15 1.25 0.20 (in.) (0.011 0.001) (0.020 0.004) (0.032 0.006) (0.049 0.008) (t) terminal mm 0.15 0.05 0.25 0.15 0.35 0.15 0.50 0.25 (in.) (0.006 0.002) (0.010 0.006) (0.014 0.006) (0.020 0.010) wvdc 10 16 25 4 6.3 10 16 25 4 6.3 10 16 25 35 6.3 10 16 25 35 50 cap 100 a (pf) 150 a 220 a 330 a 470 a 680 a 1000 a 1500 a 2200 a a 3300 a 4700 a 6800 a cap 0.010 a c (? 0.015 cg 0.022 cg 0.033 cg 0.047 cgg 0.068 cg n 0.10 c c g n 0.15 c g n 0.22 c g g n 0.33 c c g g n 0.47 c g n 0.68 c g n n 1.0 c c g g g n n 1.5 nn 2.2 gg n n 3.3 n 4.7 gg n n 6.8 10 n 22 47 100 wvdc 10 16 25 4 6.3 10 16 25 4 6.3 10 16 25 35 6.3 10 16 25 35 50 size 0201 0402 0603 0805 l w t t letter a c e g j k m n p q x y z max. 0.33 0.56 0.71 0.86 0.94 1.02 1.27 1.40 1.52 1.78 2.29 2.54 2.79 thickness (0.013) (0.022) (0.028) (0.034) (0.037) (0.040) (0.050) (0.055) (0.060) (0.070) (0.090) (0.100) (0.110) paper embossed
22 x5r dielectric capacitance range letter a c e g j k m n p q x y z max. 0.33 0.56 0.71 0.86 0.94 1.02 1.27 1.40 1.52 1.78 2.29 2.54 2.79 thickness (0.013) (0.022) (0.028) (0.034) (0.037) (0.040) (0.050) (0.055) (0.060) (0.070) (0.090) (0.100) (0.110) paper embossed preferred sizes are shaded size 1206 1210 1812 soldering reflow/wave reflow only reflow only packaging paper/embossed paper/embossed all embossed (l) length mm 3.20 0.20 3.20 0.20 4.50 0.30 (in.) (0.126 0.008) (0.126 0.008) (0.177 0.012) (w) width mm 1.60 0.20 2.50 0.20 3.20 0.20 (in.) (0.063 0.008) (0.098 0.008) (0.126 0.008) (t) terminal mm 0.50 0.25 0.50 0.25 0.61 0.36 (in.) (0.020 0.010) (0.020 0.010) (0.024 0.014) wvdc 6.3 10 16 25 35 6.3 10 16 25 35 6.3 10 25 cap 100 (pf) 150 220 330 470 680 1000 1500 2200 3300 4700 6800 cap 0.010 (? 0.015 0.022 0.033 0.047 0.068 0.10 0.15 0.22 0.33 0.47 m 0.68 1.0 q n 1.5 2.2 q q x 3.3 4.7 q q q z 6.8 10 q q q z z 22 q z z z z 47 z z 100 z wvdc 6.3 10 16 25 35 6.3 10 16 25 35 6.3 10 25 size 1206 1210 1812 l w t t
60 packaging of chip components automatic insertion packaging tape & reel quantities all tape and reel specifications are in compliance with rs481. 8mm 12mm paper or embossed carrier 0612, 0508, 0805, 1206, 1210 embossed only 1812, 1825 1808 2220, 2225 paper only 0201, 0306, 0402, 0603 qty. per reel/7" reel 2,000, 3,000 or 4,000, 10,000, 15,000 3,000 500, 1,000 contact factory for exact quantity contact factory for exact quantity qty. per reel/13" reel 5,000, 10,000, 50,000 10,000 4,000 contact factory for exact quantity reel dimensions tape a b* c d* n w 1 w 2 w 3 size (1) max. min. min. min. max. 7.90 min. 8mm 14.4 (0.311) (0.567) 10.9 max. 330 1.5 20.2 50.0 (0.429) (12.992) (0.059) (0.795) (1.969) 11.9 min. 12mm 18.4 (0.469) (0.724) 15.4 max. (0.607) metric dimensions will govern. english measurements rounded and for reference only. (1) for tape sizes 16mm and 24mm (used with chip size 3640) consult eia rs-481 latest revision. 13.0 +0.50 -0.20 (0.512 +0.020 ) -0.008 8.40 +1.5 -0.0 (0.331 +0.059 ) -0.0 12.4 +2.0 -0.0 (0.488 +0.079 ) -0.0
61 tape size b 1 d 1 e 2 fp 1 rt 2 wa 0 b 0 k 0 max. min. min. min. max. see note 5 see note 2 8mm 4.35 1.00 6.25 3.50 0.05 4.00 0.10 25.0 2.50 max. 8.30 see note 1 (0.171) (0.039) (0.246) (0.138 0.002) (0.157 0.004) (0.984) (0.098) (0.327) 12mm 8.20 1.50 10.25 5.50 0.05 4.00 0.10 30.0 6.50 max. 12.3 see note 1 (0.323) (0.059) (0.404) (0.217 0.002) (0.157 0.004) (1.181) (0.256) (0.484) 8mm 4.35 1.00 6.25 3.50 0.05 2.00 0.10 25.0 2.50 max. 8.30 see note 1 1/2 pitch (0.171) (0.039) (0.246) (0.138 0.002) (0.079 0.004) (0.984) (0.098) (0.327) 12mm 8.20 1.50 10.25 5.50 0.05 8.00 0.10 30.0 6.50 max. 12.3 see note 1 double (0.323) (0.059) (0.404) (0.217 0.002) (0.315 0.004) (1.181) (0.256) (0.484) pitch embossed carrier configuration 8 & 12mm tape only p 0 b 0 p 1 p 2 d 0 t 2 t top cover tape deformation between embossments center lines of cavity max. cavity size - see note 1 d 1 for components 2.00 mm x 1.20 mm and larger (0.079 x 0.047) 10 pitches cumulative tolerance on tape 0.2mm ( 0.008) b 1 e 1 f embossment user direction of feed e 2 w k 0 t 1 s 1 a 0 b 1 is for tape reader reference only including draft concentric around b 0 8 & 12mm embossed tape metric dimensions will govern constant dimensions variable dimensions notes: 1. the cavity defined by a 0 , b 0 , and k 0 shall be configured to provide the following: surround the component with sufficient clearance such that: a) the component does not protrude beyond the sealing plane of the cover tape. b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the cover tape has been removed. c) rotation of the component is limited to 20?maximum (see sketches d & e). d) lateral movement of the component is restricted to 0.5mm maximum (see sketch f). 2. tape with or without components shall pass around radius ??without damage. 3. bar code labeling (if required) shall be on the side of the reel opposite the round sprocket holes. refer to eia-556. 4. b 1 dimension is a reference dimension for tape feeder clearance only. 5. if p 1 = 2.0mm, the tape may not properly index in all tape feeders. tape size d 0 ep 0 p 2 s 1 min. t max. t 1 8mm 1.75 0.10 4.0 0.10 2.0 0.05 0.60 0.60 0.10 and (0.069 0.004) (0.157 0.004) (0.079 0.002) (0.024) (0.024) (0.004) 12mm max. 0.50mm (0.020) maximum 0.50mm (0.020) maximum top view, sketch "f" component lateral movements 1.50 +0.10 -0.0 (0.059 +0.004 ) -0.0 chip orientation
62 tape size p 1 e 2 min. f w a 0 b 0 t see note 4 8mm 4.00 0.10 6.25 3.50 0.05 see note 1 (0.157 0.004) (0.246) (0.138 0.002) 12mm 4.00 0.010 10.25 5.50 0.05 12.0 0.30 (0.157 0.004) (0.404) (0.217 0.002) (0.472 0.012) 8mm 2.00 0.05 6.25 3.50 0.05 1/2 pitch (0.079 0.002) (0.246) (0.138 0.002) 12mm 8.00 0.10 10.25 5.50 0.05 12.0 0.30 double (0.315 0.004) (0.404) (0.217 0.002) (0.472 0.012) pitch paper carrier configuration 8 & 12mm tape only p 0 b 0 p 1 p 2 d 0 t top cover tape bottom cover tape center lines of cavity cavity size see note 1 10 pitches cumulative tolerance on tape 0.20mm ( 0.008) e 1 f g user direction of feed e 2 w t 1 t 1 a 0 8 & 12mm paper tape metric dimensions will govern constant dimensions tape size d 0 ep 0 p 2 t 1 g. min. r min. 8mm 1.75 0.10 4.00 0.10 2.00 0.05 0.10 0.75 25.0 (0.984) and (0.069 0.004) (0.157 0.004) (0.079 0.002) (0.004) (0.030) see note 2 12mm max. min. min. variable dimensions 1.10mm (0.043) max. for paper base tape and 1.60mm (0.063) max. for non-paper base compositions notes: 1. the cavity defined by a 0 , b 0 , and t shall be configured to provide sufficient clearance surrounding the component so that: a) the component does not protrude beyond either surface of the carrier tape; b) the component can be removed from the cavity in a vertical direction without mechanical restriction after the top cover tape has been removed; c) rotation of the component is limited to 20?maximum (see sketches a & b); d) lateral movement of the component is restricted to 0.5mm maximum (see sketch c). 2. tape with or without components shall pass around radius ??without damage. 3. bar code labeling (if required) shall be on the side of the reel opposite the sprocket holes. refer to eia-556. 4. if p 1 = 2.0mm, the tape may not properly index in all tape feeders. 0.50mm (0.020) maximum 0.50mm (0.020) maximum top view, sketch "c" component lateral 1.50 +0.10 -0.0 (0.059 +0.004 ) -0.0 8.00 +0.30 -0.10 (0.315 +0.012 ) -0.004 8.00 +0.30 -0.10 (0.315 +0.012 ) -0.004 bar code labeling standard avx bar code labeling is available and follows latest version of eia-556
63 bulk case packaging case quantities part size 0402 0603 0805 1206 qty. 10,000 (t=.023") 5,000 (t=.023") (pcs / cassette) 80,000 15,000 8,000 (t=.031") 4,000 (t=.032") 6,000 (t=.043") 3,000 (t=.044") benefits bulk feeder ?easier handling ?smaller packaging volume (1/20 of t/r packaging) ?easier inventory control ?flexibility ?recyclable case dimensions shutter slider attachment base 110mm 12mm 36mm case cassette gate shooter chips expanded drawing mounter head
64 i. capacitance (farads) english: c = .224 k a t d metric: c = .0884 k a t d ii. energy stored in capacitors (joules, watt - sec) e = 1 2 cv 2 iii. linear charge of a capacitor (amperes) i = c dv dt iv. total impedance of a capacitor (ohms) z = r 2 s + (x c - x l ) 2 v. capacitive reactance (ohms) x c = 1 2 fc vi. inductive reactance (ohms) x l = 2 fl vii. phase angles: ideal capacitors: current leads voltage 90 ideal inductors: current lags voltage 90 ideal resistors: current in phase with voltage viii. dissipation factor (%) d.f.= tan (loss angle) = e.s.r. = (2 fc) (e.s.r.) x c ix. power factor (%) p.f. = sine (loss angle) = cos f (phase angle) p.f. = (when less than 10%) = df x. quality factor (dimensionless) q = cotan (loss angle) = 1 d.f. xi. equivalent series resistance (ohms) e.s.r. = (d.f.) (xc) = (d.f.) / (2 fc) xii. power loss (watts) power loss = (2 fcv 2 ) (d.f.) xiii. kva (kilowatts) kva = 2 fcv 2 x 10 -3 xiv. temperature characteristic (ppm/?) t.c. = ct ?c 25 x 10 6 c 25 (t t ?25) xv. cap drift (%) c.d. = c 1 ?c 2 x 100 c 1 xvi. reliability of ceramic capacitors l 0 = v t xt t y l t ( v o )( t o ) xvii. capacitors in series (current the same) any number: 1 = 1 + 1 --- 1 c t c 1 c 2 c n c 1 c 2 two: c t = c 1 + c 2 xviii. capacitors in parallel (voltage the same) c t = c 1 + c 2 --- + c n xix. aging rate a.r. = % d c/decade of time xx. decibels db = 20 log v 1 v 2 pico x 10 -12 nano x 10 -9 micro x 10 -6 milli x 10 -3 deci x 10 -1 deca x 10 +1 kilo x 10 +3 mega x 10 +6 giga x 10 +9 tera x 10 +12 k = dielectric constant f = frequency l t = test life a = area l = inductance v t = test voltage t d = dielectric thickness = loss angle v o = operating voltage v = voltage f = phase angle t t = test temperature t = time x & y = exponent effect of voltage and temp. t o = operating temperature r s = series resistance l o = operating life metric prefixes symbols basic capacitor formulas
65 general description formulations ? multilayer ceramic capacitors are available in both class 1 and class 2 formulations. temperature compensating formulation are class 1 and temperature stable and general application formulations are classified as class 2. class 1 ? class 1 capacitors or temperature compensating capacitors are usually made from mixtures of titanates where barium titanate is normally not a major part of the mix. they have predictable temperature coefficients and in general, do not have an aging characteristic. thus they are the most stable capacitor available. the most popular class 1 multilayer ceramic capacitors are c0g (np0) temperature compensating capacitors (negative-positive 0 ppm/?). class 2 eia class 2 capacitors typically are based on the chemistry of barium titanate and provide a wide range of capacitance values and temperature stability. the most commonly used class 2 dielectrics are x7r and y5v. the x7r provides intermediate capacitance values which vary only ?5% over the temperature range of -55? to 125?. it finds applications where stability over a wide temperature range is required. the y5v provides the highest capacitance values and is used in applications where limited temperature changes are expected. the capacitance value for y5v can vary from 22% to -82% over the -30? to 85? temperature range. all class 2 capacitors vary in capacitance value under the influence of temperature, operating voltage (both ac and dc), and frequency. for additional information on perfor- mance changes with operating conditions, consult avx? software, spicap. basic construction ? a multilayer ceramic (mlc) capaci- tor is a monolithic block of ceramic containing two sets of offset, interleaved planar electrodes that extend to two opposite surfaces of the ceramic dielectric. this simple structure requires a considerable amount of sophistication, both in material and manufacture, to produce it in the quality and quantities needed in today? electronic equipment. ceramic layer electrode terminated edge terminated edge end terminations margin electrodes multilayer ceramic capacitor figure 1
66 in specifying capacitance change with temperature for class 2 materials, eia expresses the capacitance change over an operating temperature range by a 3 symbol code. the first symbol represents the cold temperature end of the temper- ature range, the second represents the upper limit of the operating temperature range and the third symbol repre- sents the capacitance change allowed over the operating temperature range. table 1 provides a detailed explanation of the eia system. effects of voltage ? variations in voltage have little effect on class 1 dielectric but does affect the capacitance and dissipation factor of class 2 dielectrics. the application of dc voltage reduces both the capacitance and dissipation factor while the application of an ac voltage within a reasonable range tends to increase both capacitance and dissipation factor readings. if a high enough ac voltage is applied, eventually it will reduce capacitance just as a dc voltage will. figure 2 shows the effects of ac voltage. capacitor specifications specify the ac voltage at which to measure (normally 0.5 or 1 vac) and application of the wrong voltage can cause spurious readings. figure 3 gives the voltage coefficient of dissipation factor for various ac voltages at 1 kilohertz. applications of different frequencies will affect the percentage changes versus voltages. typical effect of the application of dc voltage is shown in figure 4. the voltage coefficient is more pronounced for higher k dielectrics. these figures are shown for room tem- perature conditions. the combination characteristic known as voltage temperature limits which shows the effects of rated voltage over the operating temperature range is shown in figure 5 for the military bx characteristic. general description figure 2 50 40 30 20 10 0 12.5 25 37.5 50 volts ac at 1.0 khz capacitance change percent cap. change vs. a.c. volts x7r figure 3 curve 3 - 25 vdc rated capacitor curve 2 - 50 vdc rated capacitor curve 1 - 100 vdc rated capacitor curve 3 curve 2 curve 1 .5 1.0 1.5 2.0 2.5 ac measurement volts at 1.0 khz dissipation factor percent 10.0 8.0 6.0 4.0 2.0 0 d.f. vs. a.c. measurement volts x7r eia code percent capacity change over temperature range rs198 temperature range x7 -55? to +125? x6 -55? to +105? x5 -55? to +85? y5 -30? to +85? z5 +10? to +85? code percent capacity change d ?.3% e ?.7% f ?.5% p ?0% r ?5% s ?2% t +22%, -33% u +22%, - 56% v +22%, -82% mil code symbol temperature range a -55? to +85? b -55? to +125? c -55? to +150? symbol cap. change cap. change zero volts rated volts r +15%, -15% +15%, -40% s +22%, -22% +22%, -56% w +22%, -56% +22%, -66% x +15%, -15% +15%, -25% y +30%, -70% +30%, -80% z +20%, -20% +20%, -30% table 1: eia and mil temperature stable and general application codes example ?a capacitor is desired with the capacitance value at 25? to increase no more than 7.5% or decrease no more than 7.5% from -30? to +85?. eia code will be y5f. temperature characteristic is specified by combining range and change symbols, for example br or aw. specification slash sheets indicate the characteristic applicable to a given style of capacitor.
67 general description typical cap. change vs. d.c. volts x7r typical cap. change vs. temperature x7r effects of time ? class 2 ceramic capacitors change capacitance and dissipation factor with time as well as tem- perature, voltage and frequency. this change with time is known as aging. aging is caused by a gradual re-alignment of the crystalline structure of the ceramic and produces an exponential loss in capacitance and decrease in dissipation factor versus time. a typical curve of aging rate for semi- stable ceramics is shown in figure 6. if a class 2 ceramic capacitor that has been sitting on the shelf for a period of time, is heated above its curie point, (125? for 4 hours or 150? for 1 2 hour will suffice) the part will de-age and return to its initial capacitance and dissi- pation factor readings. because the capacitance changes rapidly, immediately after de-aging, the basic capacitance measurements are normally referred to a time period some- time after the de-aging process. various manufacturers use different time bases but the most popular one is one day or twenty-four hours after ?ast heat.?change in the aging curve can be caused by the application of voltage and other stresses. the possible changes in capacitance due to de-aging by heating the unit explain why capacitance changes are allowed after test, such as temperature cycling, moisture resistance, etc., in mil specs. the application of high voltages such as dielectric withstanding voltages also tends to de-age capacitors and is why re-reading of capaci- tance after 12 or 24 hours is allowed in military specifica- tions after dielectric strength tests have been performed. effects of frequency ? frequency affects capacitance and impedance characteristics of capacitors. this effect is much more pronounced in high dielectric constant ceramic formulation than in low k formulations. avx? spicap soft- ware generates impedance, esr, series inductance, series resonant frequency and capacitance all as functions of frequency, temperature and dc bias for standard chip sizes and styles. it is available free from avx and can be down- loaded for free from avx website: www.avx.com. 25% 50% 75% 100% percent rated volts capacitance change percent 2.5 0 -2.5 -5 -7.5 -10 0vdc -55 -35 -15 +5 +25 +45 +65 +85 +105 +125 temperature degrees centigrade capacitance change percent +20 +10 0 -10 -20 -30 figure 4 figure 5 1 10 100 1000 10,000 100,000 hours capacitance change percent +1.5 0 -1.5 -3.0 -4.5 -6.0 -7.5 characteristic max. aging rate %/decade c0g (np0) x7r, x5r y5v none 2 7 figure 6 typical curve of aging rate x7r
68 effects of mechanical stress ? high ??dielectric ceramic capacitors exhibit some low level piezoelectric reactions under mechanical stress. as a general statement, the piezoelectric output is higher, the higher the dielectric constant of the ceramic. it is desirable to investigate this effect before using high ??dielectrics as coupling capaci- tors in extremely low level applications. reliability ? historically ceramic capacitors have been one of the most reliable types of capacitors in use today. the approximate formula for the reliability of a ceramic capacitor is: l o = v t x t t y l t v o t o where l o = operating life t t = test temperature and l t = test life t o = operating temperature v t = test voltage in ? v o = operating voltage x,y = see text historically for ceramic capacitors exponent x has been considered as 3. the exponent y for temperature effects typically tends to run about 8. a capacitor is a component which is capable of storing electrical energy. it consists of two conductive plates (elec- trodes) separated by insulating material which is called the dielectric. a typical formula for determining capacitance is: c = .224 ka t c = capacitance (picofarads) k = dielectric constant (vacuum = 1) a = area in square inches t = separation between the plates in inches (thickness of dielectric) .224 = conversion constant (.0884 for metric system in cm) capacitance ? the standard unit of capacitance is the farad. a capacitor has a capacitance of 1 farad when 1 coulomb charges it to 1 volt. one farad is a very large unit and most capacitors have values in the micro (10 -6 ), nano (10 -9 ) or pico (10 -12 ) farad level. dielectric constant in the formula for capacitance given above the dielectric constant of a vacuum is arbitrarily cho- sen as the number 1. dielectric constants of other materials are then compared to the dielectric constant of a vacuum. dielectric thickness ? capacitance is indirectly propor- tional to the separation between electrodes. lower voltage requirements mean thinner dielectrics and greater capaci- tance per volume. area ? capacitance is directly proportional to the area of the electrodes. since the other variables in the equation are usually set by the performance desired, area is the easiest parameter to modify to obtain a specific capacitance within a material group. energy stored ? the energy which can be stored in a capacitor is given by the formula: e = 1 2 cv 2 e = energy in joules (watts-sec) v = applied voltage c = capacitance in farads potential change ? a capacitor is a reactive component which reacts against a change in potential across it. this is shown by the equation for the linear charge of a capacitor: i ideal = c dv dt where i = current c = capacitance dv/dt = slope of voltage transition across capacitor thus an infinite current would be required to instantly change the potential across a capacitor. the amount of current a capacitor can ?ink?is determined by the above equation. equivalent circuit a capacitor, as a practical device, exhibits not only capacitance but also resistance and inductance. a simplified schematic for the equivalent circuit is: c = capacitance l = inductance r s = series resistance r p = parallel resistance reactance ? since the insulation resistance (r p ) is normal- ly very high, the total impedance of a capacitor is: z = r 2 s + (x c - x l ) 2 where z = total impedance r s = series resistance x c = capacitive reactance = 1 2 fc x l = inductive reactance = 2 fl the variation of a capacitor? impedance with frequency determines its effectiveness in many applications. phase angle ? power factor and dissipation factor are often confused since they are both measures of the loss in a capacitor under ac application and are often almost identical in value. in a ?erfect?capacitor the current in the capacitor will lead the voltage by 90? general description r l r c p s
69 general description in practice the current leads the voltage by some other phase angle due to the series resistance r s . the comple- ment of this angle is called the loss angle and: power factor (p.f.) = cos f or sine dissipation factor (d.f.) = tan for small values of the tan and sine are essentially equal which has led to the common interchangeability of the two terms in the industry. equivalent series resistance ? the term e.s.r. or equivalent series resistance combines all losses both series and parallel in a capacitor at a given frequency so that the equivalent circuit is reduced to a simple r-c series connection. dissipation factor ? the df/pf of a capacitor tells what percent of the apparent power input will turn to heat in the capacitor. dissipation factor = e.s.r. = (2 fc) (e.s.r.) x c the watts loss are: watts loss = (2 fcv 2 ) (d.f.) very low values of dissipation factor are expressed as their reciprocal for convenience. these are called the ??or quality factor of capacitors. parasitic inductance the parasitic inductance of capac- itors is becoming more and more important in the decou- pling of today? high speed digital systems. the relationship between the inductance and the ripple voltage induced on the dc voltage line can be seen from the simple inductance equation: v = l di dt the seen in current microprocessors can be as high as 0.3 a/ns, and up to 10a/ns. at 0.3 a/ns, 100ph of parasitic inductance can cause a voltage spike of 30mv. while this does not sound very drastic, with the vcc for microproces- sors decreasing at the current rate, this can be a fairly large percentage. another important, often overlooked, reason for knowing the parasitic inductance is the calculation of the resonant frequency. this can be important for high frequency, by- pass capacitors, as the resonant point will give the most signal attenuation. the resonant frequency is calculated from the simple equation: f res = 1 2 lc insulation resistance ? insulation resistance is the resistance measured across the terminals of a capacitor and consists principally of the parallel resistance r p shown in the equivalent circuit. as capacitance values and hence the area of dielectric increases, the i.r. decreases and hence the product (c x ir or rc) is often specified in ohm faradsor more commonly megohm-microfarads. leakage current is determined by dividing the rated voltage by ir (ohm? law). dielectric strength ? dielectric strength is an expression of the ability of a material to withstand an electrical stress. although dielectric strength is ordinarily expressed in volts, it is actually dependent on the thickness of the dielectric and thus is also more generically a function of volts/mil. dielectric absorption ? a capacitor does not discharge instantaneously upon application of a short circuit, but drains gradually after the capacitance proper has been dis- charged. it is common practice to measure the dielectric absorption by determining the ?eappearing voltage?which appears across a capacitor at some point in time after it has been fully discharged under short circuit conditions. corona ? corona is the ionization of air or other vapors which causes them to conduct current. it is especially prevalent in high voltage units but can occur with low volt ages as well where high voltage gradients occur. the energy discharged degrades the performance of the capacitor and can in time cause catastrophic failures. di dt f e.s.r. c
70 surface mounting guide mlc chip capacitors component pads should be designed to achieve good solder filets and minimize component movement during reflow soldering. pad designs are given below for the most common sizes of multilayer ceramic capacitors for both wave and reflow soldering. the basis of these designs is: ?pad width equal to component width. it is permissible to decrease this to as low as 85% of component width but it is not advisable to go below this. ?pad overlap 0.5mm beneath component. ?pad extension 0.5mm beyond components for reflow and 1.0mm for wave soldering. d1 d2 d3 d4 d5 case size d1 d2 d3 d4 d5 0402 1.70 (0.07) 0.60 (0.02) 0.50 (0.02) 0.60 (0.02) 0.50 (0.02) 0603 2.30 (0.09) 0.80 (0.03) 0.70 (0.03) 0.80 (0.03) 0.75 (0.03) 0805 3.00 (0.12) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 1.25 (0.05) 1206 4.00 (0.16) 1.00 (0.04) 2.00 (0.09) 1.00 (0.04) 1.60 (0.06) 1210 4.00 (0.16) 1.00 (0.04) 2.00 (0.09) 1.00 (0.04) 2.50 (0.10) 1808 5.60 (0.22) 1.00 (0.04) 3.60 (0.14) 1.00 (0.04) 2.00 (0.08) 1812 5.60 (0.22) 1.00 (0.04)) 3.60 (0.14) 1.00 (0.04) 3.00 (0.12) 1825 5.60 (0.22) 1.00 (0.04) 3.60 (0.14) 1.00 (0.04) 6.35 (0.25) 2220 6.60 (0.26) 1.00 (0.04) 4.60 (0.18) 1.00 (0.04) 5.00 (0.20) 2225 6.60 (0.26) 1.00 (0.04) 4.60 (0.18) 1.00 (0.04) 6.35 (0.25) dimensions in millimeters (inches) reflow soldering wave soldering component spacing for wave soldering components, must be spaced sufficiently far apart to avoid bridging or shadowing (inability of solder to penetrate properly into small spaces). this is less impor- tant for reflow soldering but sufficient space must be allowed to enable rework should it be required. preheat & soldering the rate of preheat should not exceed 4?/second to prevent thermal shock. a better maximum figure is about 2?/second. for capacitors size 1206 and below, with a maximum thickness of 1.25mm, it is generally permissible to allow a temperature differential from preheat to soldering of 150?. in all other cases this differential should not exceed 100?. for further specific application or process advice, please consult avx. cleaning care should be taken to ensure that the capacitors are thoroughly cleaned of flux residues especially the space beneath the capacitor. such residues may otherwise become conductive and effectively offer a low resistance bypass to the capacitor. ultrasonic cleaning is permissible, the recommended conditions being 8 watts/litre at 20-45 khz, with a process cycle of 2 minutes vapor rinse, 2 minutes immersion in the ultrasonic solvent bath and finally 2 minutes vapor rinse. d1 d2 d3 d4 d5 case size d1 d2 d3 d4 d5 0603 3.10 (0.12) 1.20 (0.05) 0.70 (0.03) 1.20 (0.05) 0.75 (0.03) 0805 4.00 (0.15) 1.50 (0.06) 1.00 (0.04) 1.50 (0.06) 1.25 (0.05) 1206 5.00 (0.19) 1.50 (0.06) 2.00 (0.09) 1.50 (0.06) 1.60 (0.06) dimensions in millimeters (inches) 1mm (0.04) 1.5mm (0.06) 1mm (0.04) component pad design
71 surface mounting guide mlc chip capacitors application notes storage good solderability is maintained for at least twelve months, provided the components are stored in their ?s received packaging at less than 40? and 70% rh. solderability terminations to be well soldered after immersion in a 60/40 tin/lead solder bath at 235 5? for 2 1 seconds. leaching terminations will resist leaching for at least the immersion times and conditions shown below. recommended soldering profiles lead-free reflow profile lead-free wave soldering the recommended peak temperature for lead-free wave soldering is 250?-260? for 3-5 seconds. the other para- meters of the profile remains the same as above. the following should be noted by customers changing from lead based systems to the new lead free pastes. a) the visual standards used for evaluation of solder joints will need to be modified as lead free joints are not as bright as with tin-lead pastes and the fillet may not be as large. b) resin color may darken slightly due to the increase in temperature required for the new pastes. c) lead-free solder pastes do not allow the same self align- ment as lead containing systems. standard mounting pads are acceptable, but machine set up may need to be modified. general surface mounting chip multilayer ceramic capacitors are designed for soldering to printed circuit boards or other substrates. the construction of the components is such that they will withstand the time/temperature profiles used in both wave and reflow soldering methods. handling chip multilayer ceramic capacitors should be handled with care to avoid damage or contamination from perspiration and skin oils. the use of tweezers or vacuum pick ups is strongly recommended for individual components. bulk handling should ensure that abrasion and mechanical shock are minimized. taped and reeled components provides the ideal medium for direct presentation to the placement machine. any mechanical shock should be minimized during handling chip multilayer ceramic capacitors. preheat it is important to avoid the possibility of thermal shock during soldering and carefully controlled preheat is therefore required. the rate of preheat should not exceed 4?/second termination type solder solder immersion time tin/lead/silver temp. ? seconds nickel barrier 60/40/0 260 5 30 1 reflow 300 250 200 150 100 50 0 solder temp. 10 sec. max 1min 1min (minimize soldering time) natural cooling 220 c to 250 c preheat wave 300 250 200 150 100 50 0 solder temp. (preheat chips before soldering) t/maximum 150 c 3 sec. max 1 to 2 min preheat natural cooling 230 c to 250 c t 300 250 200 150 100 50 0 0 50 100 150 200 250 300 pre-heating: 150 c 15 c / 60-90 s max. peak g radient 2.5 c/ s peak temperature: 245 c 5 c time at >230 c: 40 s max. temperature c time ( s )
72 surface mounting guide mlc chip capacitors and a target figure 2?/second is recommended. although an 80? to 120? temperature differential is preferred, recent developments allow a temperature differential between the component surface and the soldering temper- ature of 150? (maximum) for capacitors of 1210 size and below with a maximum thickness of 1.25mm. the user is cautioned that the risk of thermal shock increases as chip size or temperature differential increases. soldering mildly activated rosin fluxes are preferred. the minimum amount of solder to give a good joint should be used. excessive solder can lead to damage from the stresses caused by the difference in coefficients of expansion between solder, chip and substrate. avx terminations are suitable for all wave and reflow soldering systems. if hand soldering cannot be avoided, the preferred technique is the utilization of hot air soldering tools. cooling natural cooling in air is preferred, as this minimizes stresses within the soldered joint. when forced air cooling is used, cooling rate should not exceed 4?/second. quenching is not recommended but if used, maximum temperature differentials should be observed according to the preheat conditions above. cleaning flux residues may be hygroscopic or acidic and must be removed. avx mlc capacitors are acceptable for use with all of the solvents described in the specifications mil-std- 202 and eia-rs-198. alcohol based solvents are acceptable and properly controlled water cleaning systems are also acceptable. many other solvents have been proven successful, and most solvents that are acceptable to other components on circuit assemblies are equally acceptable for use with ceramic capacitors. post solder handling once smp components are soldered to the board, any bending or flexure of the pcb applies stresses to the sol- dered joints of the components. for leaded devices, the stresses are absorbed by the compliancy of the metal leads and generally don? result in problems unless the stress is large enough to fracture the soldered connection. ceramic capacitors are more susceptible to such stress because they don? have compliant leads and are brittle in nature. the most frequent failure mode is low dc resistance or short circuit. the second failure mode is significant loss of capacitance due to severing of contact between sets of the internal electrodes. cracks caused by mechanical flexure are very easily identi- fied and generally take one of the following two general forms: mechanical cracks are often hidden underneath the termi- nation and are difficult to see externally. however, if one end termination falls off during the removal process from pcb, this is one indication that the cause of failure was excessive mechanical stress due to board warping. type a: angled crack between bottom of device to top of solder joint. type b: fracture from top of device to bottom of device.
73 surface mounting guide mlc chip capacitors pcb board design to avoid many of the handling problems, avx recommends that mlcs be located at least .2" away from nearest edge of board. however when this is not possible, avx recommends that the panel be routed along the cut line, adjacent to where the mlc is located. solder tip solder tip preferred method - no direct part contact poor method - direct contact with part no stress relief for mlcs routed cut line relieves stress on mlc common causes of mechanical cracking the most common source for mechanical stress is board depanelization equipment, such as manual breakapart, v- cutters and shear presses. improperly aligned or dull cutters may cause torqueing of the pcb resulting in flex stresses being transmitted to components near the board edge. another common source of flexural stress is contact during parametric testing when test points are probed. if the pcb is allowed to flex during the test cycle, nearby ceramic capacitors may be broken. a third common source is board to board connections at vertical connectors where cables or other pcbs are con- nected to the pcb. if the board is not supported during the plug/unplug cycle, it may flex and cause damage to nearby components. special care should also be taken when handling large (>6" on a side) pcbs since they more easily flex or warp than smaller boards. reworking of mlcs thermal shock is common in mlcs that are manually attached or reworked with a soldering iron. avx strongly recommends that any reworking of mlcs be done with hot air reflow rather than soldering irons. it is practically impossi- ble to cause any thermal shock in ceramic capacitors when using hot air reflow. however direct contact by the soldering iron tip often caus- es thermal cracks that may fail at a later date. if rework by soldering iron is absolutely necessary, it is recommended that the wattage of the iron be less than 30 watts and the tip temperature be <300?. rework should be performed by applying the solder iron tip to the pad and not directly contacting any part of the ceramic capacitor.

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